Field of the Invention
The invention lies in the field of integrated technology. More specifically, the invention relates to an integrated circuit having a test circuit, and to a method for decoupling the test circuit in an integrated circuit.
During the manufacturing process of integrated circuits, such as e.g. DRAMs, a series of test measurements are necessary by means of which the functionality of the integrated circuits is checked. The tests are typically carried out after the completion of certain integration stages, e.g. after wafer production at the wafer level, after encapsulation at the component level and also in the finished system. Constituent parts of the tests usually comprise the plumbing of parameter windows, the replacement of defective circuit parts by redundant elements and also the tuning and retuning of electrical parameters with the aid of fuse devices.
The test procedures are carried out by connecting the integrated circuit to a tester device. However, in order to be able to carry out the test procedure, a series of test switching elements implemented in the integrated circuit are required. In this case, the test switching elements are usually required only for the test procedure and not in later operation in the end device. In order to save chip area and input terminals, however, the same input terminals and lines that are used for operating the circuits are used for driving the test switching elements. This has the consequence that the test switching elements impair the function of the circuits during operation because they capacitively load the lines used and consume power in the later application.
An example that may be mentioned is a current defined as IDD2N by JEDEC. The current IDD2N relates to DRAM semiconductor memories, in the case of which the semiconductor memory is in the so-called bank idle state, i.e. data are neither read from the semiconductor memory nor written to the semiconductor memory. The current IDD2N must not exceed a specific value. However, the command and address terminals of the integrated circuit are connected to a common command and address bus. In other words, even when an integrated circuit is not activated, there are applied to the input terminals signals which alternate between high states and low states but which are correspondingly intended only for one of the memory modules connected to the bus lines.
The command and address lines are typically connected to a series of test circuits. These test circuits are required for setting test modes, decoding trimming values and the like. The test circuits that are connected to the address terminals and are partly active lead to an increased capacitive load and cause an increased current IDD2N in the case of signal transitions at the address terminals. The current consumption IDD2N is intended to be kept as small as possible, however, because the maximum frequency of the command and address signals that can be achieved is reduced with larger current IDD2N.
It is accordingly an object of the invention to provide an integrated circuit which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which provides for an integrated circuit wherein the load on signal lines by the test circuits is reduced.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated circuit, comprising:
at least one functional circuit;
a test circuit for testing the functional circuit in a test procedure;
a signal line connecting the test circuit to the functional circuit; and
an isolating device connected in the signal line for physically isolating the signal line after an operation of the test circuit in the test procedure.
With the above and other objects in view there is also provided, in accordance with the invention, a decoupling method, which comprises the following steps:
providing an integrated circuit having a test circuit connected via a signal line;
initiating a test procedure in the integrated circuit with a test mode signal for the test circuit;
testing the integrated circuit with the test circuit;
terminating the test procedure; and
permanently interrupting a signal line with which the test circuit is connected.
In other words, the invention provides an integrated circuit having a test circuit, which is connected to circuits of the integrated circuit via a signal line. An isolating device is provided in the signal line in order to physically, i.e. completely, isolate the signal line after the operation of the test circuit in a test procedure.
One advantage of the present invention is that an integrated circuit is provided with the possibility of completely disconnecting the test circuit from the corresponding signal lines once it is no longer required for a test procedure or the like. Complete isolation is to be understood preferably not as a controlled switching, but rather as a galvanic isolation such as e.g. an interruption of a connecting line.
What can be achieved in this way is that the test circuit or associated circuit parts are no longer connected as load to the corresponding input terminals if they are not needed again during conventional operation of the integrated circuit. Compared with an electrical isolation by a switchable semiconductor element, such as e.g. a transistor, the advantage in a complete (galvanic) isolation is that essentially no capacitive load on account of the connected test circuits remains on the signal lines. In contrast to this, with a transistor as isolating element, there is always a capacitance formed by the active semiconductor junction area.
Preferably, the isolating device is situated at addressing, data or command terminals of a semiconductor memory or of a logic circuit and/or at one or more of the supply voltage terminals. The isolating device is preferably configured in such a way that it has a fuse device. Fuse devices are quite generally provided in order to effect settings for an integrated circuit, they are used, for example, for replacing defective memory cells by redundant memory cells, by setting parameters in the integrated circuit, or the like. The fuse device may have, for example, a laser fuse and/or an electrical fuse. Laser fuses are initially closed connections which are interrupted with the aid of a laser beam. In the case of electrical fuses, an interconnect is severed by electric current in the fuse process by applying a high voltage. The use of a fuse device has the advantage that a complete physical isolation of a line connection can be carried out, so that only a very small, negligible residual capacitance remains.
A further aspect of the present invention provides a method for decoupling a test circuit in an integrated circuit. After the starting of a test procedure in the integrated circuit by provision of a test mode signal for the test circuit e.g. by a test device, the integrated circuit is tested. After the ending of the test procedure, a signal line which connects the test circuit to one or more signal lines is permanently interrupted.
What is thereby achieved is that the test circuit is permanently and completely isolated from the input terminals and the rest of the circuits in the integrated circuit. In this way, the capacitive load which a test circuit connected to a signal line exerts on the signal line can be considerably reduced.
Preferably, the isolation of the signal line by e.g. a programming current is carried out substantially in temporal proximity to or in the same process step wherein a further line is interrupted by an isolating device in the integrated circuit. This enables the interruption of signal lines to be integrated into an already existing process of interruption of lines by isolating devices, e.g. fuse devices, so that a possibly time-consuming additional method step can be avoided. Moreover, in the same process step wherein the isolation of the signal line is carried out, a connecting device for producing a line connection, in particular an antifuse device, can also be through-connected. Antifuses are through-connected by applying a programming current, i.e. antifuses are initially nonconducting and are turned into a conducting connection by application of a programming current.
It may be provided that, in a process step during the fabrication of a memory circuit wherein fuse devices are separated for replacing defective memory blocks by redundant memory blocks, the signal lines to which a test circuit for ascertaining the defective memory blocks is connected are simultaneously interrupted.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated circuit having a test circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.